The End of Legacy Tools? Partcl’s Boson Redefines Static Timing Analysis
Partcl is a next-generation chip design automation startup founded in 2025 in San Francisco. With a mission to modernize Electronic Design Automation (EDA) using GPU acceleration and AI, the company is setting new benchmarks in speed and efficiency. The startup's signature product, Boson, delivers up to 700x performance improvements over traditional static timing analysis tools, a feat that's already drawing the attention of elite VLSI researchers and chipmakers alike.
Backed by Y Combinator, and founded by Vamshi Balanaga and William Salcedo, Partcl is on a path to transform the way semiconductors are designed — leveraging deep physics knowledge, AI-driven optimization, and blistering GPU power to solve one of the industry’s most critical bottlenecks.
Why Is Chip Design Ready for Disruption?
Despite decades of innovation in semiconductor performance and miniaturization, many EDA tools still rely on architectures and workflows from the 1990s. As chip complexity increases — driven by demands from AI, cloud computing, and consumer electronics — engineers often spend weeks wrestling with legacy software that lacks modern performance and flexibility.
This is especially problematic in timing analysis, a fundamental step in verifying a chip’s speed and logic correctness. Traditional tools are not only slow, but they also struggle to scale efficiently for modern chip architectures with millions of gates and tight time-to-market constraints.
Partcl was founded after its co-founders experienced this pain firsthand. After spending countless hours troubleshooting legacy tools ahead of high-stakes tapeouts, they asked themselves a simple question: What if we redesigned EDA from the ground up for the 21st century?
What Makes Boson So Fast?
At the core of Partcl’s product suite is Boson, a GPU-accelerated Static Timing Analysis (STA) engine. Boson uses physics-informed models and advanced parallelization strategies to dramatically reduce computation times.
Benchmarks speak for themselves:
- 100k gate netlist: 400 milliseconds
- 1M gate netlist: 1 second
- 7M gate netlist: 3 seconds
These numbers represent a 700x speedup over traditional STA tools — a transformation that turns previously overnight computations into real-time feedback loops. This not only accelerates development cycles but also enables chip designers to explore many more design alternatives within the same time frame.
Who Is Behind Partcl?
Partcl was founded by Vamshi Balanaga and William Salcedo, both of whom bring deep expertise in chip design, software engineering, and high-performance computing. Their academic roots stretch across Cornell, UC Berkeley, and Stanford, while their professional experiences span tech titans like Amazon, Apple, and Nvidia — as well as several hardware-focused startups.
Their frustration with outdated EDA workflows during late-stage chip design at past roles became the genesis of Partcl. With backing from Y Combinator and guidance from leading VLSI researchers, the duo is committed to making cutting-edge chip design tools accessible, fast, and AI-integrated.
How Can AI and GPUs Transform EDA?
Partcl’s philosophy centers around one powerful idea: EDA tools should be AI-native and GPU-first. Traditional EDA systems often struggle with scalability due to their CPU-bound, sequential architectures. By contrast, modern GPUs offer thousands of cores that are ideal for the massive parallelism required in chip simulations and analysis.
Moreover, AI-driven design space exploration has become increasingly important in optimizing performance, power, and area (PPA) in complex chips. But without fast feedback from simulation and timing tools, this optimization loop becomes impractically slow. Partcl's tools enable real-time design iteration, making AI-assisted optimization not just viable, but transformative.
What Problems Does Boson Solve for Engineers?
Chip engineers are under constant pressure to meet tight deadlines while managing increasingly complex designs. With conventional tools, static timing analysis is not only slow but often unreliable at advanced nodes (7nm and below), leading to last-minute surprises that can delay tapeout or degrade product performance.
Boson gives engineers an edge by offering:
- Speed: No more waiting hours (or days) for results
- Scalability: Handles millions of gates with ease
- Modern architecture: Built for GPUs and AI from the ground up
- Real-time iteration: Enables faster experimentation and debugging
This leap in performance can save weeks of engineering time, reduce costly errors, and help teams hit ambitious go-to-market schedules.
Who Can Use Boson Today?
Partcl is currently offering early access to Boson and actively working with industry and academic partners. The tool is especially valuable for:
- Chip design startups that need to move fast
- Large enterprises modernizing their toolchains
- Academic researchers pushing the frontiers of VLSI
Recognizing the importance of academic contributions to EDA innovation, Partcl offers heavily discounted access for universities and research institutions.
What Process Nodes Does Partcl Support?
Partcl currently supports chip designs at 7nm and above, with more advanced nodes in development. This makes it immediately useful for a wide range of current-generation semiconductors, including those used in mobile processors, AI accelerators, and networking chips.
As the company grows, its roadmap includes expanding support for 5nm and 3nm technologies, ensuring that Partcl’s tools remain future-ready for the most demanding designs.
What’s Next for Partcl?
While Boson is already changing how engineers think about timing analysis, the team at Partcl isn’t stopping there. They're actively working on an integrated placement and resizing tool to further speed up chip optimization workflows. This addition will allow engineers to not only verify timing faster but also tweak layouts and parameters for optimal results, all within a tightly integrated toolchain.
By bridging static timing with placement, Partcl aims to unlock a closed-loop optimization system — one where AI can rapidly test and refine millions of possible configurations with immediate feedback from Boson and its future companion tools.
Why Does Partcl Matter Right Now?
As the world increasingly relies on semiconductors — from AI to electric vehicles to space tech — the demand for faster, smarter chip design tools has never been higher. The industry is entering an era where tapeout delays and suboptimal designs can cost millions, if not billions, in lost opportunity.
Partcl is building for this future. Its tools reduce friction, shorten cycles, and empower teams to explore the full potential of their hardware ideas. In doing so, the startup isn’t just accelerating design — it’s unlocking a new era of AI-enhanced semiconductor innovation.
How Is Partcl Redefining the Future of EDA?
By reimagining Electronic Design Automation with GPU acceleration and AI-native workflows, Partcl is doing more than improving performance — it's setting a new standard for what chip design can look like. The company’s goal is clear: to help engineers build better chips, faster, and with fewer compromises.
In the words of the founding team, “We want chip designers to benefit from the AI revolution.” And with Boson, they’ve built a compelling argument that the future of EDA is no longer on the horizon — it’s already here.